1. Field of the Invention
This invention generally relates to data processing systems and more specifically to a method for obtaining quantitative analyses of the operation of input/output devices.
2. Description of Related Art
Large data processing systems often include multiple central processors and a large primary mass storage device, typically a direct access storage device (DASD). Applications that run on such systems demand high performance, particularly input/output (I/O) transfer rates that include transferring to and from the direct access storage device. As I/O transfer rate requirements become more demanding, DASD manufacturers strive to improve performance by altering hardware and control designs. Given the sophistication of current DASD architecture, it becomes highly advantageous to pretest prototype systems using such design modifications by means of various benchmark testing procedures to evaluate the overall impact of a design change on overall performance. This has led to the development of evaluation or benchmark methods.
United States Letters Patent No. 5,088,058 to Salsburg, for example, discloses an apparatus and method for evaluating and predicting computer I/O performance using I/O work load snapshots for a model input. The evaluation and prediction is based upon a simulation model that contains a stack constructed such that delays are formulated as sets of stochastic processes. The simulation model includes at least one statistical sub-model and has delay parameters that are settable in accordance with a selectable I/O disk configuration. A selectable I/O work load snapshot grouped into I/O batches drives the simulation model that then provides both overall and batch output data in response to the I/O work load snapshot. In addition, the simulation model takes into account the presence of cache storage in the selected I/O configuration.
While the foregoing evaluation method predicts I/O rates, it is even more important to quantify the effect of different designs on actual I/O rates. The methods for making actual measurements during such an evaluation are very important, particularly in large systems such as IBM based systems utilizing the multiple virtual storage (MVS) concept. However, the measurements can become difficult to implement, primarily because the MVS system can establish hundreds of address spaces for different applications that produce data transfers by means of an I/O subsystem that relies upon a task control block (TCB) and a supervisory request block (SRB) with a requirement that contention among the blocks be resolved before an associated task or source can be processed.
One prior art approach to obtaining an I/O benchmark in an MVS-based system has been to generate independent I/O operations in each device in a direct access storage device, such as a Symmetrix Series 5500 integrated cached disk array available from the assignee of this invention. In such an integrated cached disk array a "device" is a "logical volume". In the context of MVS an I/O benchmark test for such a cached disk array uses one TCB per device. Conventional MVS systems serialize any contentions by such processes for common locks that are in an MVS address space. This is a serialization process that prevents one process running under one TCB from running until a previously selected process running under another TCB in that address space has been completed. At normal input/output rates with a few devices the overhead introduced by the time required to resolve the contentions represented by multiple lock/unlock operations is small in comparison with the interval between I/O operations.
Certain DASD architectures, such as the Symmetrix Series 5500 integrated cached disk array architecture, can build large capacity memories for many small disk controllers and associated physical disk drives configured into 100 or more logical volumes, or devices. However, it has been found that when more than thirty-two separate devices are involved, the time required for the MVS system to resolve contentions for access to an address space by processes running under corresponding task control blocks becomes significant in comparison with I/O times. The resulting delays required to resolve contentions can skew results so the benchmark test does not provide reliable measurements. This problem is exacerbated as the number of devices increases beyond thirty-two as the time to resolve contention varies as the square of the number of devices. As a result, the prior art tends to impose a limit of 32 devices, or whatever the maximum number that can be accommodated by the I/O benchmark without unacceptable delay. If the total number of devices exceeds such a maximum, unacceptable delays are avoided by running multiple copies of the benchmark in parallel in different address spaces. For example, if the integrated cached disk array contains 128 logical volumes or devices, four copies of the I/O benchmark will run in parallel under the MVS operating system thereby to assure the maximum acceptable TCB count in a single address space. Such parallel operations introduce further complexities in the benchmark than can detract from objectives of the benchmark.